EVAL: Utilizing processors with variation-induced timing errors

Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case parameter values, we may lose substantial performance. An alternate approach explored in this paper is to design for closer to nominal values, and provide some transistor budget to tolerate unavoidable variationinduced errors. To assess this approach, this paper first presents a novel framework that shows how microarchitecture techniques can trade off variation-induced errors for power and processor frequency. Then, the paper introduces an effective technique to maximize performance and minimize power in the presence of variationinduced errors, namely High-Dimensional dynamic adaptation. For efficiency, the technique is implemented using a machinelearning algorithm. The results show that our best configuration increases processor frequency by 56% on average, allowing the processor to cycle 21% faster than with...

• Type: Conference
• Year: 2008
• Where: MICRO
• Authors: Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas
• Keywords: Hardware, MICRO 2008, Processor Frequency, Unavoidable Variationinduced Errors, Worst-case Parameter Values