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HICSS
1996
IEEE

Evaluation of Parallel Logic Simulation Using DVSIM

9 years 6 months ago
Evaluation of Parallel Logic Simulation Using DVSIM
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulation algorithms. The framework's core is DVSIM, a parallel event-driven VHDL simulator. The framework provides several mechanisms to calculate sensible bases for speed-up calculation. Monitoring tools are employed to observe and to improve the algorithmic performance. A rst implementation of DVSIM used a conservative synchronization method, but a Time Warp protocol has recently been completed. In uencing factors for speed-up such as partitioning and mapping methods are discussed. Experience shows that even with conservative synchronization schemes moderate speed-ups can be obtained for larger circuits. The speed-up values are compared to theoretically possible acceleration factors, and the reasons why these ideal maximum speed-up values can in general not be reached are explained.
Gerd Meister
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where HICSS
Authors Gerd Meister
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