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Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores

10 years 3 months ago
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
Semiconductor manufacturers aim at deliver new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended to be a companion for processor cores. The proposed I-IP is an efficient, low-cost and easy-to-adopt solution for supporting the silicon debug of microprocessor cores and of other cores in a SoC, as it reuses the hardware introduced for implementing processor Software-Based Self Test (SBST).
Paolo Bernardi, Michelangelo Grosso, Maurizio Reba
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where MTV
Authors Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda
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