Failure-Sensitive Analysis of Parallel Algorithms with Controlled Memory Access Concurrency

ract problem of using P failure-prone processors to cooperatively update all locations of an N-element shared array is called Write-All. Solutions to Write-All can be used iteratively to construct efficient simulations of pram algorithms on failureams. Such use of Write-All in simulations is abstracted in terms of the iterative Write-All problem. The efficiency of the algorithmic solutions for Write-All and iterative Write-All is measured in terms of work complexity where all processing steps taken by the processors are counted. This paper considers determinitic solutions for the WriteAll and iterative Write-All problems in the fail-stop synchronous crcw pram model where memory access concurrency needs to be controlled. A deterministic algorithm of Kanellakis, Michailidis, and Shvartsman [16] efficiently solves the Write-All problem in this model, while controlling read and write memory access concurrency. However it was not shown how the number of processor failures f affects the wo...

• Type: Journal
• Year: 2007
• Where: PPL
• Authors: Chryssis Georgiou, Alexander Russell, Alexander A. Shvartsman
• Keywords: Iterative Write-all, Iterative Write-all Problems, Memory Access, PPL 2007