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ISCA
2012
IEEE
248views Hardware» more  ISCA 2012»
7 years 17 days ago
Watchdog: Hardware for safe and secure manual memory management and full memory safety
Languages such as C and C++ use unsafe manual memory management, allowing simple bugs (i.e., accesses to an object after deallocation) to become the root cause of exploitable secu...
Santosh Nagarakatte, Milo M. K. Martin, Steve Zdan...
PDP
2011
IEEE
8 years 1 months ago
Accelerating Parameter Sweep Applications Using CUDA
—This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications w...
Masaya Motokubota, Fumihiko Ino, Kenichi Hagihara
MICRO
2011
IEEE
407views Hardware» more  MICRO 2011»
8 years 5 months ago
Thread Cluster Memory Scheduling
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
MICRO
2010
IEEE
210views Hardware» more  MICRO 2010»
8 years 8 months ago
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
TPDS
2010
98views more  TPDS 2010»
8 years 8 months ago
The Synchronization Power of Coalesced Memory Accesses
—Multicore architectures have established themselves as the new generation of computer architectures. As part of the one core to many cores evolution, memory access mechanisms ha...
Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus
VLSISP
2008
147views more  VLSISP 2008»
8 years 8 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
PPL
2007
86views more  PPL 2007»
8 years 9 months ago
Failure-Sensitive Analysis of Parallel Algorithms with Controlled Memory Access Concurrency
ract problem of using P failure-prone processors to cooperatively update all locations of an N-element shared array is called Write-All. Solutions to Write-All can be used iterati...
Chryssis Georgiou, Alexander Russell, Alexander A....
VLDB
2002
ACM
108views Database» more  VLDB 2002»
8 years 9 months ago
Generic Database Cost Models for Hierarchical Memory Systems
Accurate prediction of operator execution time is a prerequisite for database query optimization. Although extensively studied for conventional disk-based DBMSs, cost modeling in ...
Stefan Manegold, Peter A. Boncz, Martin L. Kersten
CORR
2006
Springer
112views Education» more  CORR 2006»
8 years 10 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
SERP
2003
8 years 11 months ago
Memory Access Characteristics of Network Infrastructure Applications
Network infrastructure is composed of various devices located either in the core or at the edges of a wide-area network. These devices are required to deliver high transaction thr...
Abdul Waheed
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