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FPGA
2014
ACM

Fast and effective placement and routing directed high-level synthesis for FPGAs

4 years 10 months ago
Fast and effective placement and routing directed high-level synthesis for FPGAs
Achievable frequency (fmax) is a widely used input constraint for designs targeting Field-Programmable Gate Arrays (FPGA), because of its impact on design latency and throughput. fmax is limited by critical path delay, which is highly influenced by lower-level details of the circuit implementation such as technology mapping, placement and routing. However, for high-level synthesis (HLS) design flows, it is challenging to evaluate the real critical delay at the behavioral level. Current HLS flows typically use module pre-characterization for delay estimates. However, we will demonstrate that such delay estimates are not sufficient to obtain high fmax and also minimize total execution latency. In this paper, we introduce a new HLS flow that integrates with Altera’s Quartus synthesis and fast placement and routing (PAR) tool to obtain realistic post-PAR delay estimates. This integration enables an iterative flow that improves the performance of the design with both behaviorallevel...
Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, De
Added 19 May 2015
Updated 19 May 2015
Type Journal
Year 2014
Where FPGA
Authors Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen
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