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ICCAD
1998
IEEE

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

10 years 7 months ago
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The algorithm can be easily modified to give exact algorithms for optimizing several other objectives (e.g., minimizing maximum delay or minimizing total area subject to arrival time specifications at all inputs and outputs). No previous algorithm for simultaneous gate and wire sizing can guarantee exact solutions for general circuits. Our algorithm is an iterative one with a guarantee on convergence to global optimal solutions. It is based on Lagrangian relaxation and "one-gate/wire-at-atime" greedy optimizations, and is extremely economical and fast. For example, we can optimize a circuit with 27 648 gates and
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1998
Where ICCAD
Authors Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
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