Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System

– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for duplex system design, each including the combination of totally self-checking blocks based on parity predictors to obtain better dependability parameters. Combinatorial circuit benchmarks have been considered in all our experiments and computations. A Totally Self-Checking analysis of duplex system is supported by experimental results from our proposed FPGA fault simulator, where SEU-fault resistance is observed. Our proposed hardware fault simulator is compared also with the software simulation. An area overhead of individual parts implemented in each FPGA is also discussed.

• Type: Conference
• Year: 2007
• Where: DDECS
• Authors: Pavel Kubalík, Jirí Kvasnicka, Hana Kubatova
• Keywords: DDECS 2007, Fault Simulation Technique, Fault Simulator, FPGA, Hardware