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2008
ACM

Filtering drowsy instruction cache to achieve better efficiency

9 years 11 months ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed period of time, only a small subset of cache lines is used. Previous techniques put unused lines, for example, to drowsy in order to save power. Our idea is to adaptively select the most used cache lines. In the case of instruction cache, we found that this can automatically achieved by coupling a tiny cache acting as a filter cache (IL0 cache) with a drowsy-cache. Our experiments, with complete MiBench suite for ARM based processor, show a 25% improvement in leakage saving versus drowsy. Categories and Subject Descriptors B.3.2 [Memory structures]: Design styles
Roberto Giorgi, Paolo Bennati
Added 28 Dec 2010
Updated 28 Dec 2010
Type Journal
Year 2008
Where SAC
Authors Roberto Giorgi, Paolo Bennati
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