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2007
IEEE

Fine grain 3D integration for microarchitecture design through cube packing exploration

11 years 3 months ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose techniques that enable efficient exploration of the 3D design space where each logical block can span more than one silicon layers. Although further power and performance improvement is achievable through fine grain 3D integration, the necessary modeling and tool infrastructure has been mostly missing. We develop a cube packing engine which can simultaneously optimize physical and architectural design for effective utilization of 3D in terms of performance, area and temperature. Our experimental results using a design driver show 36% performance improvement (in BIPS) over 2D and 14% over 3D with single layer blocks. Additionally multi-layer blocks can provide up to 30% reduction in power dissipation compared to the single-layer alternatives. Peak temperature of the design is kept within limits as a result of ther...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2007
Where ICCD
Authors Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong
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