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2006
IEEE

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

10 years 5 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to operate the processor within a given power envelope. These techniques, however, often lead to high-frequency current variations, which can stress the power delivery system and jeopardize reliability due to inductive noise (L di dt ) in the power supply network. To counteract these issues, modern microprocessors are designed to operate under the worst-case current assumption by deploying adequate decoupling capacitance. With the trend of lower supply voltage and increased leakage power and current consumption, designing a processor for the worst case is becoming less appealing. In this paper, we propose a new dynamic inductive-noise controlling mech...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where MICRO
Authors Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee
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