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13

CAV
1990
Springer

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Formal Verification of Digital Circuits Using Symbolic Ternary System Models

13 years 8 months ago

Formal Verification of Digital Circuits Using Symbolic Ternary System Models

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Ternary system modeling involves extending the traditional set of binary values

Randal E. Bryant, Carl-Johan H. Seger

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CAV 1990 | Circuit Phenomena | Hardware | Synchronous Digital Circuits | Ternary Symbolic Simulator |

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Added	10 Aug 2010
Updated	10 Aug 2010
Type	Conference
Year	1990
Where	CAV
Authors	Randal E. Bryant, Carl-Johan H. Seger

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