Sciweavers

Share
ISCAS
2007
IEEE

A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider

9 years 5 months ago
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ∆Σ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high frequencies. Hence, a low oversampling ratio (OSR) ∆Σ fractional-N PLL can be achieved without increasing quantization noise. Architecture comparison and simulation results are also presented.
Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang
Comments (0)
books