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2008
IEEE

Generalised Parallel Bilinear Interpolation Architecture for Vision Systems

12 years 3 months ago
Generalised Parallel Bilinear Interpolation Architecture for Vision Systems
Bilinear interpolation is widely used in computer vision for extracting pixel values for positions that lie off the pixel grid in an image. For each sub-pixel, the values of four neighbours are used to compute the interpolated value. This presents a challenge since four pixels must be read from the source image memory for each output pixel. This paper presents an architecture, for implementation within FPGAbased vision systems, that takes advantage of the heterogeneous resources available on modern devices to parallelise these memory accesses through efficient distribution of the source image in embedded memories. We show how intrinsic information in the sub-pixel addresses can be used to implement bilinear interpolation efficiently. We then suggest modifications to the architecture for larger image sizes which exceed the memory capabilities of modern FPGAs. The architecture is shown to achieve performance of 250Msamples per second in a modern device.
Suhaib A. Fahmy
Added 01 Jun 2010
Updated 01 Jun 2010
Type Conference
Year 2008
Where RECONFIG
Authors Suhaib A. Fahmy
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