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AHS
2006
IEEE

Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures

13 years 9 months ago
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures
Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+λ) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures.
Emanuele Stomeo, Tatiana Kalganova, Cyrille Lamber
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where AHS
Authors Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert
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