Sciweavers

Share
SASO
2009
IEEE

Generic Self-Adaptation to Reduce Design Effort for System-on-Chip

10 years 6 months ago
Generic Self-Adaptation to Reduce Design Effort for System-on-Chip
We investigate a generic self-adaptation method to reduce the design effort for System-on-Chip (SoC). Previous self-adaptation solutions at chip-level use circuitries which have been specially designed for the current problem by hand, leading to an elaborate and inflexible design process, requiring specially trained engineers, and making design reuse difficult. On the other hand, a generic self-adaptation method that can be used for various self-adaptation problems promises to reduce the necessary design effort, but may come with reduced performance and other costs. In this paper, we analyze the performance, self-adaptation capabilities and costs of a generic self-adaptation method. The proposed method allows chip-level self-adaptation of a SoC, can tolerate unforeseen events, and can generalize from previous self-adaptation tasks. Furthermore, the method helps to improve the design process by allowing design reuse, providing generic applicability, and offering a uniform design proc...
Andreas Bernauer, Oliver Bringmann, Wolfgang Rosen
Added 21 May 2010
Updated 21 May 2010
Type Conference
Year 2009
Where SASO
Authors Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
Comments (0)
books