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2003
IEEE

Hardware Partitioning Software for Dynamically Reconfigurable SoC Design

11 years 4 months ago
Hardware Partitioning Software for Dynamically Reconfigurable SoC Design
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibilities of reconfiguration that the FPGA component can offer. Here, we present a temporal hardware partitioning software, included in a design methodology, that uses the reconfiguration possibilities of the FPGA for the SOC system design. This automated partitioning tool minimises the number of cells needed to implement an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resource needs. It can also be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.
Philippe Brunet, Camel Tanougast, Yves Berviller,
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where IWSOC
Authors Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber
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