Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography

Until now, most cryptography implementations on parallel architectures have focused on adapting the software to SIMD architectures initially meant for media applications. In this paper, we review some of the most significant contributions in this area. We then propose a vector architecture to efficiently implement long precision modular multiplications. Having such a data level parallel hardware provides a circuit whose decode and schedule units are at least of the same complexity as those of a scalar processor. The excess transistors are mainly found in the data path. Moreover, the vector approach gives a very modular architecture where resources can be easily redefined. We built a functional simulator onto which we performed a quantitative analysis to study how the resizing of those resources affects the performance of the modular multiplication operation. Hence we not only propose a vector architecture for our Public Key cryptographic operations but also show how we can analyze the...

• Type: Conference
• Year: 2006
• Where: DSD
• Authors: Jacques J. A. Fournier, Simon W. Moore
• Keywords: Architecture, DSD 2006, Hardware, Modular Multiplication, Vector Architecture