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2003
IEEE

Heterogeneous Programmable Logic Block Architectures

10 years 9 months ago
Heterogeneous Programmable Logic Block Architectures
In this poster, we propose four new heterogeneous programmable logic blocks (PLBs) consisting of a combination of various sizes of look up tables (LUTs), multiplexers (MUXes), and logic gates. We demonstrate that these PLBs offer significant performance and density benefits over more homogeneous PLBs.
Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Cheta
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where DATE
Authors Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
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