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SAMOS
2015
Springer

A high-level DRAM timing, power and area exploration tool

3 years 1 months ago
A high-level DRAM timing, power and area exploration tool
—In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Evaluating the impact of DRAM design decisions therefore requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload which requires a full system simulator, running a complete software stack. In this paper, we introduce DRAMSpec, an open source high-level DRAM bank modeling tool. As major contribution, the DRAM modeling abstraction level from detailed circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (nonDRAM experts) to tune future DRAM architectures for their target applications and use cas...
Omar Naji, Christian Weis, Matthias Jung 0001, Nor
Added 17 Apr 2016
Updated 17 Apr 2016
Type Journal
Year 2015
Where SAMOS
Authors Omar Naji, Christian Weis, Matthias Jung 0001, Norbert Wehn, Andreas Hansson
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