High-level power analysis for on-chip networks

13 years 10 months ago

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As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design ﬂow of such systems. With power increasingly the primary constraint in chips, the tool chain in systems design, from simulation infrastructures to compilers and synthesis frameworks, needs to take network power into account, motivating the need for early-stage communication power analysis. While there has been substantial research in network performance analysis that enabled critical insights into network design, no power analysis frameworks for networks exist. In this paper, we propose such a framework that takes as input message ﬂows, and derives a power proﬁle of the network fabric, capturing both the spatial variance across the network fabric as well as the temporal variance across application execution time. Our analysis is based utilization as the unit of abstraction for network power, with contention among message ﬂows modeled th...

Noel Eisley, Li-Shiuan Peh

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