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ISCAS
2007
IEEE

High Speed 1-bit Bypass Adder Design for Low Precision Additions

9 years 5 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture adopts 8-bit processing units as the atomic operation. Hence, high speed 8-bit adders are a key building block necessary for high performance. The proposed adder intends to speed up 8-bit adder operations. It is based on a conventional bypass adder scheme, but bypasses 2 bits on every adder bit stage rather than bypassing 4 bits on every four bit stages for conventional bypass adders. The proposed adder enables high speed operation for the FleXilicon and maximizes sub-word parallelism. The proposed adder is implemented with full custom design in CMOS 65 nm process. Simulation results show that the proposed adder is two times faster than existing adders for 8 bit additions.
Jong-Suk Lee, Dong Sam Ha
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Jong-Suk Lee, Dong Sam Ha
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