6 search results - page 1 / 2 » High Speed 1-bit Bypass Adder Design for Low Precision Addit... |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
ARITH
2009
IEEE
13 years 11 months ago
2009
IEEE
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
ICCD
1997
IEEE
13 years 8 months ago
1997
IEEE
Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions ...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...