A High-Speed Clockless Serial Link Transceiver

We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with high-speed, serial off-chip buses. While synchronous transceivers commonly use multi-phase clocks to control the data multiplexing and demultiplexing, our clockless transceiver uses a token-ring architecture that eliminates complex clock generation and synchronization circuitry. Furthermore, our clockless receiver dynamically self-adjusts its sampling rate to match the bit rate of the transmitter. Our SPICE simulations report that in a 0.18µm CMOS technology this transceiver design operates at

• Type: Conference
• Year: 2003
• Where: ASYNC
• Authors: John Teifel, Rajit Manohar
• Keywords: ASYNC 2003, Clockless Transceiver, Hardware, Serial Link Transceivers, Serial Off-chip Buses