ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
Parameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
We describe the Lutonium, an asynchronous 8051 microcontroller designed for optimal ؾ . In 0.18- m CMOS, at nominal
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
High-speed asynchronous ripple FIFOs may be easily embedded in synchronous environments and can elegantly handle the problem of forwarding data between clock domains. In cases whe...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, t...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...