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ISCAS
2005
IEEE

A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter

9 years 4 months ago
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the gated lateral npn or pnp BJT inherent of nor p-channel MOSFETs. Forward current is applied to the base terminal of the channel MOSFETs, with a normal pull-up or pull-down MOSFET as a current source, where each drain terminal is connected to the corresponding base terminal of the inverter. A logic scheme is also proposed to control the gates of the pull-up or pull-down MOSFETs in switching states using output signals made from two CMOS inverters with different resistance ratios. Circuit simulation using 0.35 µm BSIM3v3 model parameters for MOSFETs and a current gain of βF =100 for BJTs, the speed of a domino CMOS full adder with the U
Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISCAS
Authors Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga
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