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EUROPAR
2000
Springer

Impact of PE Mapping on Cray T3E Message-Passing Performance

10 years 7 months ago
Impact of PE Mapping on Cray T3E Message-Passing Performance
The aim of this paper is to study the influence of processor mapping on message passing performance of two different parallel computers: the Cray T3E and the SGI Origin 2000. For this purpose, we have first designed an experiment where processors are paired off in a random manner and messages are exchanged between them. In view of the results of this experiment, it is obvious that the physical placement must be accounted for. Consequently, a mapping algorithm for the Cray T3E, suited cartesian topologies is studied. We conclude by making comparisons between our T3E algorithm, the MPI default mapping and another algorithm proposed by M
Eduardo Huedo, Manuel Prieto, Ignacio Martí
Added 24 Aug 2010
Updated 24 Aug 2010
Type Conference
Year 2000
Where EUROPAR
Authors Eduardo Huedo, Manuel Prieto, Ignacio Martín Llorente, Francisco Tirado
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