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FPL
2007
Springer

Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

13 years 9 months ago
Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core
This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium R processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.
Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molde
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where FPL
Authors Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit
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