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FPL
2007
Springer
98views Hardware» more  FPL 2007»
10 years 6 months ago
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
Shannon Koh, Oliver Diessel
FPL
2007
Springer
97views Hardware» more  FPL 2007»
10 years 8 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
FPL
2007
Springer
150views Hardware» more  FPL 2007»
10 years 8 months ago
Discrete Event Simulation of Molecular Dynamics with Configurable Logic
: Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretized ...
Josh Model, Martin C. Herbordt
FPL
2007
Springer
122views Hardware» more  FPL 2007»
10 years 8 months ago
Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97)
Jamshid Shokrollahi, Elisa Gorla, Christoph Puttma...
FPL
2007
Springer
99views Hardware» more  FPL 2007»
10 years 8 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
FPL
2007
Springer
80views Hardware» more  FPL 2007»
10 years 10 months ago
Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing
Peter M. Athanas, J. Bowen, T. Dunham, Cameron Pat...
FPL
2007
Springer
140views Hardware» more  FPL 2007»
10 years 10 months ago
An area-efficient alternative to adaptive median filtering in FPGAs
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the saltand-pepper noise of high intensity (up to 70% of corrupted pix...
Zdenek Vasícek, Lukás Sekanina
FPL
2007
Springer
124views Hardware» more  FPL 2007»
10 years 10 months ago
A Quantitative Prediction Model for Hardware/Software Partitioning
An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spo...
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Ga...
FPL
2007
Springer
141views Hardware» more  FPL 2007»
10 years 10 months ago
Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration
The effect of kernel operations on cache optimisations in a soft-core reconfigurable system is important for dynamic cache switching design. Considering kernel operations changes ...
John Shield, Peter Sutton, Philip Machanick
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