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CHES
2005
Springer

Improved Higher-Order Side-Channel Attacks with FPGA Experiments

10 years 5 months ago
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
We demonstrate that masking a block cipher implementation does not sufficiently improve its security against side-channel attacks. Under exactly the same hypotheses as in a Differential Power Analysis (DPA), we describe an improvement of the previously introduced higherorder techniques allowing us to defeat masked implementations in a low (i.e. practically tractable) number of measurements. The proposed technique is based on the efficient use of the statistical distributions of the power consumption in an actual design. It is confirmed both by theoretical predictions and practical experiments against FPGA devices.
Eric Peeters, François-Xavier Standaert, Ni
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where CHES
Authors Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater
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