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EUROPAR
2004
Springer

Improving Data Cache Performance via Address Correlation: An Upper Bound Study

9 years 5 months ago
Improving Data Cache Performance via Address Correlation: An Upper Bound Study
Address correlation is a technique that links the addresses that reference the same data values. Using a detailed source-code level analysis, a recent study [1] revealed that different addresses containing the same data can often be correlated at run-time to eliminate on-chip data cache misses. In this paper, we study the upper-bound performance of an Address Correlation System (ACS), and discuss specific optimizations for a realistic hardware implementation. An ACS can effectively eliminate most of the L1 data cache misses by supplying the data from a correlated address already found in the cache to thereby improve the performance of the processor. For 10 of the SPEC CPU2000 benchmarks, 57 to 99% of all L1 data cache load misses can be eliminated, which produces an increase of 0 to 243% in the overall performance of a superscalar processor. We also show that an ACS with 1-2 correlations for a value can usually provide comparable performance results to that of the upper bound. Furtherm...
Peng-fei Chuang, Resit Sendag, David J. Lilja
Added 01 Jul 2010
Updated 01 Jul 2010
Type Conference
Year 2004
Where EUROPAR
Authors Peng-fei Chuang, Resit Sendag, David J. Lilja
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