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PATMOS
2010
Springer
8 years 8 months ago
L1 Data Cache Power Reduction Using a Forwarding Predictor
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
P. Carazo, R. Apolloni, Fernando Castro, Daniel Ch...
TVLSI
2008
150views more  TVLSI 2008»
8 years 9 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
ISCAPDCS
2004
8 years 11 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
DSD
2008
IEEE
108views Hardware» more  DSD 2008»
9 years 3 days ago
Reducing Leakage through Filter Cache
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
Roberto Giorgi, Paolo Bennati
CF
2005
ACM
9 years 9 days ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
ICS
1995
Tsinghua U.
9 years 1 months ago
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
Antonio González, Carlos Aliagas, Mateo Val...
ENC
2004
IEEE
9 years 2 months ago
A New Cache Approach Based on Graph for Web Servers
This article deals with the problem of data cache for dynamic web servers. A set of requests (which number could be large) is submitted to a server for computing. Every request is...
Euloge Edi, Denis Trystram, Jean-Marc Vincent
DATE
2004
IEEE
177views Hardware» more  DATE 2004»
9 years 2 months ago
Adaptive Prefetching for Multimedia Applications in Embedded Systems
This paper presents a new and simple prefetching mechanism to improve the memory performance of multimedia applications. This method adapts the memory access mechanism to the acce...
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
CASES
2007
ACM
9 years 2 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
ISSS
1996
IEEE
123views Hardware» more  ISSS 1996»
9 years 2 months ago
Memory Organization for Improved Data Cache Performance in Embedded Processors
Code generation for embedded processors creates opportunities for several performance optimizations not applicable for traditional compilers. We present techniques for improving d...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
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