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ICCAD
2009
IEEE

Iterative layering: Optimizing arithmetic circuits by structuring the information flow

9 years 1 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs and outputs. Many optimizers, therefore employ libraries of hand-optimized arithmetic components, but cannot optimize across component boundaries. To remedy this situation, we introduce a new logic synthesis algorithm which analyzes the input circuit based on its behavior on a set of random assignments of input variables, and outputs a structural implementation of the input circuit. The method presented here is similar to the covering algorithm used in multi-level optimizations [4]; however, it is not based on Sum-of-Product form, or any specific input representation. Our experiments show that our approach is not only capable of automatically reproducing some known architectural implementations without any prior knowledge about the functionality of the circuit, but also, in some cases, it is able to discover ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
Added 18 Feb 2011
Updated 18 Feb 2011
Type Journal
Year 2009
Where ICCAD
Authors Ajay K. Verma, Philip Brisk, Paolo Ienne
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