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ISMVL
2003
IEEE

Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space

9 years 11 months ago
Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space
This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary threedimensional logic circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of areaspecific circuits using ISID has been demonstrated. The new method is useful for the synthesis of functions using three-dimensional regular logic circuits whenever volume-specific layout constraints have to be satisfied.
Anas Al-Rabadi
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISMVL
Authors Anas Al-Rabadi
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