Library Compatible Ceff for Gate-Level Timing

Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed using the concept of an effective capacitance, Ceff. Most published algorithms for Ceff, however, require special cell characterization or supplemental information that is not part of standard timing libraries. In this paper we present a novel Ceff algorithm that is strictly compatible with existing timing libraries. It is also fast, easily implemented, and quite accurate— within 3% of transistor-level simulation in our tests. The method is based on approximating a gate by a current source, estimating the delay difference when the gate drives the actual RC load and a reference capacitor, and then converting the delay discrepancy into a Ceff value. Central to carrying out this program is the innovative concept of delay correction transfer function.

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Bernard N. Sheehan
• Keywords: DATE 2002, Gate-level Static Timing, Hardware, Rc Load, Timing Libraries