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DATE
2002
IEEE
91views Hardware» more  DATE 2002»
9 years 3 days ago
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees
After the discussion on the difference between floorplanning and packing in VLSI placement design, this paper adapts the floorplanner that is based on the Q-sequence to a packin...
Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, ...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
9 years 3 days ago
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of ...
Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie...
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
9 years 3 days ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
DATE
2002
IEEE
146views Hardware» more  DATE 2002»
9 years 3 days ago
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The meth...
Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, A...
DATE
2002
IEEE
158views Hardware» more  DATE 2002»
9 years 3 days ago
Congestion Estimation with Buffer Planning in Floorplan Design
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Yo...
DATE
2002
IEEE
103views Hardware» more  DATE 2002»
9 years 3 days ago
Communication Mechanisms for Parallel DSP Systems on a Chip
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...
Joseph Williams, Nevin Heintze, Bryan D. Ackland
DATE
2002
IEEE
77views Hardware» more  DATE 2002»
9 years 3 days ago
A Signature Test Framework for Rapid Production Testing of RF Circuits
Production test costs for today’s RF circuits are rapidly escalating. Two factors are responsible for this cost escalation: (a) the high cost of RF ATEs and (b) long test times ...
Ramakrishna Voorakaranam, Sasikumar Cherubal, Abhi...
DATE
2002
IEEE
90views Hardware» more  DATE 2002»
9 years 3 days ago
FPGA Placement by Thermodynamic Combinatorial Optimization
Juan de Vicente, Juan Lanchares, Román Herm...
DATE
2002
IEEE
79views Hardware» more  DATE 2002»
9 years 3 days ago
Incremental Diagnosis and Correction of Multiple Faults and Errors
An incremental simulation-based approach to fault diagnosis and logic debugging is presented. During each iteration of the algorithm, a single suspicious location is identified a...
Andreas G. Veneris, Jiang Brandon Liu, Mandana Ami...
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
9 years 3 days ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
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