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ISQED
2007
IEEE

On-Line Adjustable Buffering for Runtime Power Reduction

9 years 4 months ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream technique to exploit the tradeoff. Physical design, specifically repeater insertion and sizing, is naturally signed-off at the highest performance mode. We observe that through simple modifications to the repeaters (buffers and inverters), it is possible to dynamically customize the repeater driving capacity of the design. This customization opens the door to a novel opportunity for on-line power-performance tradeoff: customizable repeaters can trade away performance for reductions in power, or vice versa. We describe a simple customization of repeaters to have an additional adjustable lowpower operation mode besides their regular operational mode. Using selective logic remapping, we demonstrate how to use the new customized repeaters in a design flow that does not impact the high-performance signoff, yet ...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
Added 04 Jun 2010
Updated 30 Aug 2010
Type Conference
Year 2007
Where ISQED
Authors Andrew B. Kahng, Sherief Reda, Puneet Sharma
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