Sciweavers

DATE
2004
IEEE
151views Hardware» more  DATE 2004»
13 years 8 months ago
Boosting: Min-Cut Placement with Improved Signal Delay
In this work we improve top-down min-cut placers in the context of timing closure. Using the concept of boosting factors, we adjust net weights according to net spans, so as to re...
Andrew B. Kahng, Igor L. Markov, Sherief Reda
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 8 months ago
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?
Michael Kadin, Sherief Reda, Augustus K. Uht
ISQED
2002
IEEE
175views Hardware» more  ISQED 2002»
13 years 9 months ago
On the Relation between SAT and BDDs for Equivalence Checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
Sherief Reda, Rolf Drechsler, Alex Orailoglu