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7

ICCAD
2004
IEEE

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Logical effort based technology mapping

14 years 1 months ago

Logical effort based technology mapping

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We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the loaddistribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.

Shrirang K. Karandikar, Sachin S. Sapatnekar

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Benchmark Circuits | Fanout-free Circuits | Hardware | ICCAD 2004 | Library-based Technology Mapping |

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Added	16 Mar 2010
Updated	16 Mar 2010
Type	Conference
Year	2004
Where	ICCAD
Authors	Shrirang K. Karandikar, Sachin S. Sapatnekar

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