Sciweavers

116 search results - page 1 / 24
» Logical effort based technology mapping
Sort
View
ICCAD
2004
IEEE
123views Hardware» more  ICCAD 2004»
14 years 1 months ago
Logical effort based technology mapping
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
Shrirang K. Karandikar, Sachin S. Sapatnekar
PATMOS
2004
Springer
13 years 10 months ago
Physical Extension of the Logical Effort Model
Abstract. The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the...
B. Lasbouygues, Robin Wilson, Philippe Maurine, Na...
ESWS
2004
Springer
13 years 10 months ago
The HCONE Approach to Ontology Merging
Existing efforts on ontology mapping, alignment and merging vary from methodological and theoretical frameworks, to methods and tools that support the semi-automatic coordination o...
Konstantinos Kotis, George A. Vouros
DAC
1994
ACM
13 years 9 months ago
Technology Mapping Using Fuzzy Logic
- This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring l...
Sasan Iman, Massoud Pedram, Kamal Chaudhary
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
13 years 10 months ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren