Sciweavers

Share
ISCAS
2006
IEEE

A low complexity hardware architecture for motion estimation

10 years 1 months ago
A low complexity hardware architecture for motion estimation
This paper tackles the problem of accelerating The rest of this paper is organised as follows: section II motion estimation for video processing. A novel architecture details related prior research. Section III proposes a new binary using binary data is proposed, which attempts to reduce power motion estimation routine which exploits early termination consumption. The solution exploits redundant operations in the sum of absolute differences (SAD) calculation, by a mechanism properties in the distorton metric calculaton and exploits known as early termination. Further data redundancies are redundancies in the binary data with a run length coding exploited by using a run length coding addressing scheme, where (RLC) addressing scheme. Section IV details an associated access to pixels which do not contribute to the final SAD value is hardware architecture. Section V details hardware synthesis minimised. By using these two techniques operations and memory results and power consumption estim...
Daniel Larkin, Vlenti. Muresan, Noel E. O'Connor
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where ISCAS
Authors Daniel Larkin, Vlenti. Muresan, Noel E. O'Connor
Comments (0)
books