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2008
IEEE

Low-complexity high-speed 4-D TCM decoder

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Low-complexity high-speed 4-D TCM decoder
This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture for the transition metrics unit (TMU) is proposed to significantly reduce the computation complexity without degrading the performance. In addition, pipelining and parallel processing techniques are exploited to increase the decoding throughput. Synthesis results show that the FPGA implementation of the TCM decoder can
Jinjin He, Zhongfeng Wang, Huaping Liu
Added 01 Jun 2010
Updated 01 Jun 2010
Type Conference
Year 2008
Where SIPS
Authors Jinjin He, Zhongfeng Wang, Huaping Liu
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