Sciweavers

Share
CCECE
2011
IEEE

A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting

8 years 6 months ago
A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting
—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first
Kambiz Nanbakhsh, Hamidreza Maghami, Samad Sheikha
Added 13 Dec 2011
Updated 13 Dec 2011
Type Journal
Year 2011
Where CCECE
Authors Kambiz Nanbakhsh, Hamidreza Maghami, Samad Sheikhaei, Nasser Masoumi, Pedram Payandehnia
Comments (0)
books