A low-power monolithically stacked 3D-TCAM

—This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithically stacked 3D-IC technology for the implementation, because vertical stacking can drastically reduce interconnect length in both matchlines and searchlines, hence reducing signal path delay and power consumption. The second technique is to replace the conventional SRAM memory in a TCAM with an array of programmable vias (or electrolyte non-volatile memory). Special programming circuitry is designed to read/write memory bits from/to the programmable via array because they do not simply store data in the form of low and high voltage levels. We also devised a new TCAM cell design to further reduce power consumption in TCAMs by taking full advantage of 3D-IC technology. A 1024×144-bit TCAM using the proposed

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Mingjie Lin, Jianying Luo, Yaling Ma
• Keywords: 3D-IC Technology, Hardware, ISCAS 2008, Power Consumption, Reduce Power Consumption