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2008
IEEE

Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip

8 years 9 months ago
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip
Systems on chip (SoC) have much in common with traditional (networked) distributed systems in that they consist of largely independent components with dedicated communication interfaces. Therefore the adoption of classic distributed algorithms for SoCs suggests itself. The implementation complexity of these algorithms, however, significantly depends on the underlying failure models. In traditional software-based solutions this is normally not an issue, such that the most unconstrained, namely the Byzantine, failure model is often applied here. Our case study of a hardwareimplemented tick synchronization algorithm shows, however, that in an SoC-implementation substantial hardware savings can result from restricting the failure model to benign failures (omissions, crashes). On the downside, it turns out that such restricted failure models have a fairly poor coverage with respect to the hardware faults occurring in practice, and that additional measures to enforce these restrictions may...
Gottfried Fuchs, Matthias Függer, Ulrich Schm
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DSD
Authors Gottfried Fuchs, Matthias Függer, Ulrich Schmid, Andreas Steininger
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