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TCAD
2010

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

7 years 11 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be ach...
Adán Kohler, Gert Schley, Martin Radetzki
Added 21 May 2011
Updated 21 May 2011
Type Journal
Year 2010
Where TCAD
Authors Adán Kohler, Gert Schley, Martin Radetzki
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