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ICC
2007
IEEE

A Memory Unit for Priority Management in IPSec Accelerators

8 years 11 months ago
A Memory Unit for Priority Management in IPSec Accelerators
— This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support Quality of Service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.
Luigi Dadda, Alberto Ferrante, Marco Macchetti
Added 03 Jun 2010
Updated 03 Jun 2010
Type Conference
Year 2007
Where ICC
Authors Luigi Dadda, Alberto Ferrante, Marco Macchetti
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