Sciweavers

5 search results - page 1 / 1
» A Memory Unit for Priority Management in IPSec Accelerators
Sort
View
ICC
2007
IEEE
127views Communications» more  ICC 2007»
13 years 11 months ago
A Memory Unit for Priority Management in IPSec Accelerators
— This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at d...
Luigi Dadda, Alberto Ferrante, Marco Macchetti
IPPS
2010
IEEE
13 years 2 months ago
A GPU-inspired soft processor for high-throughput acceleration
There is building interest in using FPGAs as accelerators for high-performance computing, but existing systems for programming them are so far inadequate. In this paper we propose...
Jeffrey Kingyens, J. Gregory Steffan
IPPS
2005
IEEE
13 years 10 months ago
Enhancing NIC Performance for MPI using Processing-in-Memory
Processing-in-Memory (PIM) technology encompasses a range of research leveraging a tight coupling of memory and processing. The most unique features of the technology are extremel...
Arun Rodrigues, Richard C. Murphy, Ron Brightwell,...
MM
2004
ACM
147views Multimedia» more  MM 2004»
13 years 10 months ago
Implementation and evaluation of EXT3NS multimedia file system
The EXT3NS is a scalable file system designed to handle video streaming workload in large-scale on-demand streaming services. It is based on a special H/W device, called Network-S...
Baik-Song Ahn, Sung-Hoon Sohn, Chei-Yol Kim, Gyu-I...
EUROPAR
2009
Springer
13 years 8 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...