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ICCD
2006
IEEE

Microarchitecture and Performance Analysis of Godson-2 SMT Processor

11 years 1 months ago
Microarchitecture and Performance Analysis of Godson-2 SMT Processor
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-of-order execution high performance processor. The condition for implementing correct memory consistency model in Godson-2 SMT processor is studied and a new register-level sharing and synchronization scheme is proposed. Godson-2 SMT processor has been implemented at the RTL level and simulated with the VstationPro of Mentor Graphics. The Linux operating system is ported to run in Godson-2 SMT processor and application programs such as SPEC CPU2000 benchmark suite are used to evaluate performance. Experimental results indicate that the performance of Godson-2 SMT processor is improved significantly by fully exploiting thread-level parallelism and optimized utilization of functional units. The average speedup is
Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2006
Where ICCD
Authors Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang
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