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2008
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A Module Checking Based Converter Synthesis Approach for SoCs

11 years 4 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We investigate this problem in a formal setting and propose, for the first time, a temporal logic based automatic solution to convertibility verification and synthesis. At its core, our technique is based on local module checking and determines the existence of the converter and if a converter exists, it is automatically generated. A number of key features of our technique distinguishes it from all existing formal and/or informal approaches. Firstly, we handle both data and control mismatches using a single unifying module checking based solution. Secondly, the proposed approach uses temporal logic for the specification of correct behaviors (unlike earlier automaton based specifications) which is both elegant and natural to express event ordering and data-matching requirements. Finally, we have experimented extensivel...
Roopak Sinha, Partha S. Roop, Samik Basu
Added 30 Nov 2009
Updated 30 Nov 2009
Type Conference
Year 2008
Where VLSID
Authors Roopak Sinha, Partha S. Roop, Samik Basu
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